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features ? smart card interface ? compliance with iso 7816, emv2000, gie-cb, gsm and whql standards card clock stop high or low for card power-down modes support synchronous cards with c4 and c8 contacts card detection and automatic de-activation sequence programmable activation sequence ? direct connection to the smart card logic level shifters short circuit current limitation (s ee electrical characteristics) 8kv+ esd protection (mil/std 883 class 3) ? programmable voltage 5v 5% at 65 ma (class a) 3v 0.2v at 65 ma (class b) 1.8v 0.14v at 40 ma ? low ripple noise: < 200 mv ? versatile host interface ? icam (conditional access) compatible ? two wire interface (twi) link programmable address allow up to 8 devices ? programmable interrupt output ? automatic level shifter (1.6v to v cc ) ? reset output includes ? power-on reset (por) ? power-fail detector (pfd) ? high-efficiency step-up converter: 80 to 98% efficiency ? extended voltage operation: 3v to 5.5v ? low power consumption ? 180 ma maximum in-rush current ? 30 a typical power-down current (without smart card) ? 4 to 48 mhz clock input, 7 mhz min for step-up converter (for at83c24) ? 18 to 48mhz clock input (for at83c24nds) ? industrial temperature range: -40 to +85 c ? packages: so28 and qfn28 description the at83c24 is a smart card reader interfac e ic for smart card reader/writer applica - tions such as eft/pos terminals and set top boxes. it enables the management of any type of smart card from any kind of host. up to 8 at83c24 can be connected in parallel using the programmable twi address. its high efficiency dc/dc converter, low quiescent current in standby mode makes it particularly suited to low power and portable applications. the reduced bill of material allows reducing significantly the system cost. a sophisticated protection system guar - antees timely and controlled shutdown upon error conditions. the at83c24nds is a dedicated version approved by nds for use with nds video - guard conditional access software in set-top boxes. all at83c24 datasheet is applicable to at83c24nds. the main differences between at83c24 and at83c24nds are listed below: 1/ class a card supplied with cvcc = 4.75 to 5.25v for at83c24nds, class a card supplied with cvcc = 4.6 to 5.25v for at83c24 2/ 18mhz minimum on input clock for at83c24nds 3/ up to 10f for capacitor connected on cvcc pin for at83c24, 3.3f mandatory for at83c24nds smart card reader interface with power management at83c24b at83c24nds 4234f?scr?10/05
2 4234f?scr?10/05 at83c24 acronyms twi: two-wire interface por: power on reset pfd: power fail detect art: automatic reset transition atr: answer to reset msb: most significant bit lsb: least significant bit scib: smart card interface bus block diagram pres/ int clk vss crst cpres cio, cc4, cc8 cclk cvcc li reset voltage supervisor por/pfd twi controller clocks controller dc/dc converter analog drivers scl sda i/o, c4, c8 dvcc evcc a2/ck, a1/rst, a0/3v, cmdvcc timer 16 bits main control & logic unit cvss cvccin vcc
3 4234f?scr?10/05 at83c24 pin description pinouts (top view) 28-pin soic pinout qfn28 pinout note: 1. nc = not connected 2. soic and qfn packages are available for at83c24 and for at83c24nds signals a1 a2 a0 1 evcc cclk crst scl vcc reset cvss cvccin i/o clk 2 3 4 5 6 7 8 9 10 28 27 26 25 24 23 22 21 20 19 li pres/int dvcc vss sda cpres 12 18 17 11 c8 cio c4 16 15 cc8 cmdvcc cc4 1 vss v cc cvss li 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 17 18 19 20 21 22 23 24 25 26 27 28 top view qfn 28 cio cc8 cvccin crst cpres cc4 cclk cmdvcc reset dvcc c8 clk pres/int c4 /ck /ck /rst a0 /rst /3v /3v cvcc cvcc sda scl a1 a2 i/o evcc 13 14 nc nc nc nc table 1. ports description pad name pad internal power supply esd limits pad type description a2/ck- a1/rst- a0/3v evcc 3 kv i microcontroller interface function: twi bus slave address selection input. a2/ck and a1/rst pins are respectively connected to cclk and crst signals in ?transparent mode? (see page 17 ). a0/3v is used for hardware activation to select cvcc voltage (3v or 5v). the slave address of the dev ice is based on the value present on a2, a1, a0 on the rising edge of reset pin (see ta b l e 2 ). in fact, the address is taken internally at the 11th clk rising edge. pres/ int evcc 3 kv o open- drain microcontroller interface function: depending on it_sel value (see config4 register), pres/ int outputs card presence status or interruptions ( page 9 ) an internal pull-up (typ 330k , see table 18 )to evcc can be activated in the pad if necessary using int_pullup bit (config4 register). remark: during power up and before registers configuration, the pres/ int signal must be ignored. reset vcc 3 kv i/o open- drain microcontroller interface function: ? power-on reset ? a low level on this pin keeps the at83c24 under reset even if applied on power-on. it also resets the at83c24 if applied when the at83c24 is running (see power monitoring ). ? asserting reset when the chip is in shut-down mode returns the chip to normal operation. ? at83c24 is driving the reset pin low on power-on-reset or if power fail on v cc or dvcc (see powermon bit in config4 regist er), this can be used to reset or interrupt other devices. after reset, at83c24 needs to be reconfigured before starting a new card session.
4 4234f?scr?10/05 at83c24 sda vcc 3 kv i/o open- drain microcontroller interface function twi serial data scl vcc 3 kv i/o open- drain microcontroller interface function twi serial clock i/o evcc 3 kv i/o microcontroller interface function copy of cio pin and high level reference for evcc. an external pull up to evcc is needed on io pin. i/o is the reference level for evcc if evcc is connected to a capacitor. this feature is unused if evcc is connected to vcc. c4 evcc 3 kv i/o (pull-up) microcontroller interface function copy of card cc4. c8 evcc 3 kv i/o (pull-up) microcontroller interface function copy of card cc8. clk evcc 3 kv i microcontroller interface function master clock cio cvcc 8 kv+ i/o (pull-up) smart card interface function card i/o cc4 cvcc 8 kv+ i/o (pull-up) smart card interface function card c4 cc8 cvcc 8 kv+ i/o (pull-up) smart card interface function card c8 cpres vcc 8 kv+ i (pull-up) smart card interface function card presence an internal pull-up to vcc can be activated in the pad if necessary using pullup bit (config1 register). cclk cvcc 8 kv+ o smart card interface function card clock crst cvcc 8 kv+ o smart card interface function card reset cmdvcc evcc 3 kv+ i (pull-up) microcontroller interface function: activation/shutdown of the smart card interface. vcc 3 kv+ pwr supply voltage v cc is used to power the internal voltage regulators and i/o buffers. li 3 kv+ pwr dc/dc input li must be tied to vcc pin through an external coil (typically 4.7 h) and provides the current for the charge pump of the dc/dc converter. it may be directly connected to vcc if the st ep-up converter is not used (see stepreg bit in config4 register and see minimum vcc values in table 20 (class a) and table 21 (class b)). table 1. ports description (continued) pad name pad internal power supply esd limits pad type description
5 4234f?scr?10/05 at83c24 note: esd test conditions: 3 positive and 3 negativ e pulses on each pin versus gnd. pulses generated according to mil/std 883 class3. recommended capacitors soldered on cvcc and vcc pins. cvcc 8 kv+ pwr card supply voltage cvcc is the programmable voltage output for the card interface. it must be connected to external decoupling capacitors (see page 34 and page 36 ). cvccin 8 kv+ pwr card supply voltage this pin must be connected to cvcc. dvcc 3 kv+ pwr digital supply voltage is internally generated and used to supply the digital core. this pin has to be connected to an exte rnal capacitor of 100 nf and should not be connected to other devices. evcc 3 kv+ pwr extra supply voltage (microcontroller power supply) evcc is used to supply the internal le vel shifters of host interface pins. evcc voltage can be supplied from the exter nal evcc pin connected to the host power supply. if evcc cannot be connected to the host power supply, it must be tied to an external capacitor. evcc voltage can be generated inter nally by an automatic follow up of the logic high level on the i/o pin. in this configuration, connect a 100 nf + 100kohms in parallel between evcc pin and vss pin. cvss 8 kv+ gnd dc/dc ground cvss is used to sink high shunt currents from the external coil. vss gnd ground table 1. ports description (continued) pad name pad internal power supply esd limits pad type description
6 4234f?scr?10/05 at83c24 operational modes twi bus control the atmel two-wire interface (twi) interconnects components on a unique two-wire bus, made up of one clock line and one data line with spe eds of up to 400 kbits per second, based on a byte-oriented transfer format. the twi-bus interface can be used: ? to configure the at83c24 ? to select the operating mode of the card: 1.8v, 3v or 5v ? to configure the automatic activation sequence ? to start or stop sessions (activat ion and de-activation sequences) ? to initiate a warm reset ? to control the clock to the card in active mode ? to control the clock to the card in stand-by mode (stop low, stop high or running) ? to enter or leave the card stand-by or power-down modes ? to select the interface (connection to the host i/o / c4/ c8) ? to request the status (card present or no t, over-current and out of range supply voltage occurrence) ? to drive and monitor the card contacts by software ? to accurately measure the atr delay when automatic activation is used twi commands frame structure the structure of the twi bus data frames is made of one or a series of write and read com - mands completed by stop. write commands to the at83c24 have the structure: address byte + command byte + data byte(s) read commands to the at83c24 have the structure: address byte + data byte(s) the address byte is sampled on a2/ck, a1/rst , a0/3v after each re set (hard/soft/general call) but a2/ck, a1/rst, a0/3v can be used for transparent mode after the reset. figure 1. data transfer on twi bus sda scl start condition stop condition 1234 5 6 78 9 acknowledgement from slave adresse byte command and/or data
7 4234f?scr?10/05 at83c24 address byte the first byte to send to the device is the add ress byte. the device controls if the hardware address (a2/ck, a1/rst, a0/3v pins on reset) corresponds to the address given in the address byte (a2, a1, a0 bits). if the level is not stable on a2/ck pin (or a1/rst pin, or a0/3v pin) at reset, the user has to send the commands to the possible address taken by the device. if a2/ck to a0/3v are tied to the host microcontroller and their reset values are unknown, a gen - eral call on the twi bus allows to reset al l the at83c24 devices and set their address after a2/ck to a0/3v are fixed. figure 2. address byte up to 8 devices can be connected on the same twi bus. each device is configured with a differ - ent combination on a2/ck, a1/rst, a0/3v pins. the corresponding address byte values for read/write operations are listed below. table 2. address byte values a2 (a2/ck pin) a1 (a1/rst pin) a0 (a0/3v pin) address byte for read command address byte for write command 0 0 0 0x41 0x40 0 0 1 0x43 0x42 0 1 0 0x45 0x44 0 1 1 0x47 0x46 1 0 0 0x49 0x48 1 0 1 0x4b 0x4a 1 1 0 0x4d 0x4c 1 1 1 0x4f 0x4e b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 0 a2 a1 a0 r/w slave address on 7 bits 1 for read command 0 for write command
8 4234f?scr?10/05 at83c24 write commands the write commands are: 1. reset: initializes all the logic and the twi interface as after a power-up or power-fail reset. if a smart card is active when reset falls, a deacti vation sequence is perf ormed. this is a one- byte command. 2. write config: configures the device according to the last six bits in the config0 register and to the fol - lowing four bytes in config1, config2, config3 then conf ig4 registers. this is a five bytes command. figure 3. command byte format for write config0 command 3. write timer: program the 16-bit automatic rese t transition timer with the fo llowing two bytes. this is a three bytes command. 4. write interface: program the interface. this is a one-byte co mmand. the msb of the command byte is fixed at 0. 5. general call reset: a general call followed by the value 06h has the same effect as a reset command. table 3. write commands description address byte (see table 2) command byte data byte 1 data byte 2 data byte 3 data byte 4 1. reset 0100 a 2 a 1 a 0 0 1111 1111 2. write config 0100 a 2 a 1 a 0 0 (10 + config0 6 bits) config1 config2 config3 config4 3. write timer 0100 a 2 a 1 a 0 0 1111 1100 timer1 timer0 4. write interface 0100 a 2 a 1 a 0 0 (0+interface 7 bits) 5. general call reset 0000 0000 0000 0110 b7 b6 b5 b4 b3 b2 b1 1 x 0 x x x x config0 on 6 bits b0 x
9 4234f?scr?10/05 at83c24 read command after the slave address has been configured, the read command allows to read one or several bytes in the following order: ? status, config0, config1, config2, config3, inte rface, timer1, timer0, capture1, capture0 ? ffh is completing the transfer if the microcon troller attempts to read beyond the last byte. note: flags are only reset after the corresponding byte read has been acknowledged by the master. table 4. read command description interrupts the pres/ int behavior depends on it_sel bit value (see config4 register). ? if it_sel= 0, the pres/ int output is high by default (on chip pull up or open drain). pres/ int is driven low by any of the following event: ? insert bit set in config0 register (card insertion/extraction or bit set by software ) ? vcard_int bit set in status register (the dc/dc output voltage has settled) ? over-current detection on cvcc ? vcarderr bit set in config0 register (out of range voltage on cvcc or bit set by software) ? atrerr bit set in config0 register (no atr before the card clock counter overflows or bit set by software).this control of atr timing is only available if art bit =1. if it_sel=0, a read command of status register and of config0 register will release pres/ int pin to high level. several at83c24 devices can share the same in terrupt and the microcontroller can identify the interrupt sources by pollin g the status of the at83c2 4 devices using twi commands. ? if it_sel= 1 (mandatory for nds applications and for software comp atibility with existing devices) the pres/ int output is high to indicate a card is present and none of the following event has occured: byte description byte value address byte 0100 a 2 a 1 a 0 1 data byte 1 status data byte 2 config0 data byte 3 config1 data byte 4 config2 data byte 5 config3 data byte 6 config4 data byte 7 interface data byte 8 timer 1 (msb) data byte 9 timer 0 (lsb) data byte 10 capture 1 (msb) data byte 11 capture 0 (lsb) data byte 12 0xff
10 4234f?scr?10/05 at83c24 ? over-current detection on cvcc ? vcarderr bit set in config0 register (out of range voltage on cvcc or bit set by software) card presence detection the card presence is provided by the cpres pi n. the polarity of card presence contact is selected with the carddet bit (see config1 regi ster). a programmable filtering is controlled with the cds[2-0] bits (see config1 register). an internal pull-up on the cpres pin can be disco nnected in order to reduce the consumption, an external pull-up must then be connected to vcc. the pullup bit (s ee config1 register) controls this feature. the card presence switch is usually connected to vss (card present if cpres=1). the card - det bit must be set. the internal pull up can be connected. if the card presence contact is connected to vc c (card present if cpres=0), the internal pull-up must be disconnected (see pullup bit) and an external pull-down must be connected to the cpres pin. an interrupt can be generated if a card is inserted or extracted (see interrupts ). figure 4. card presence input pullup bit carddet bit = 1 closed = 0 open = 1 no card if cpres = 0 = 0 no card if cpres = 1 cardin bit = 1 card inserted = 0 no card it controller cpres pres/int filtering cds[2-0] vcc int_pullup bit = 1 closed = 0 open evcc it_sel bit (see table 18) card presence contact vcc vcc card presence contact vss vss external pull-up external pull-down internal pull-up
11 4234f?scr?10/05 at83c24 cio, cc4, cc8 controller the cio, cc4, cc8 output pins are driven re spectively by cardio, cardc4, cardc8 bits values or by i/o, c4, c8 signal pins. this sele ction depends of the iodis bit value. if iodis is reset, data are bidirectional between respective ly i/o, c4, c8 pins and cio, cc4, cc8 pins. figure 5. cio, cc4, cc8 block diagram io and cio pins are linked together through the on chip level shifters if iodis bit=0 in inter - face register. this is done automati cally during an hardware activation. their iddle level are 1. with io high, cio is pulled up. the same behavior is applicable on c4/ cc4 and c8/ cc8 pins. the maximum frequency on those lines depends on clk frequency (3 clock rising edges to transfer). with clk=27mhz, the maximum frequency on this line is 1.5mhz. due to the minimum transfer delay allowed for nds applications, the clk minimum frequency is 18mhz. clock controller the clock controller generates two clocks (as shown in figure 6 and figure 7 ): 1. a clock for the cclk: four different sources can be used: clk pin, dcclk signal, cardck bit or a2/ck pin (in transparent mode). 2. a clock for dc/dc converter. cio 0 1 0 1 cardio bit cc4 cc8 0 1 cardc8 bit iodis bit cardc4 bit i/o c4 c8 cvcc cvcc cvcc evcc evcc
12 4234f?scr?10/05 at83c24 figure 6. clock block diagram with software activation (see page 14 ) figure 7. clock block diagram with hardware activation (see page 14 ) crst controller the crst output pin is driven by the a1/rst pi n signal pin or by the cardrst bit value. this selection depends of the crst_sel bit value (see config4 register). if the crst pin signal is driven by the ca rdrst bit value, two modes are available: ? if the art bit is reset, crst pin is driven by cardrst bit. ? if the art bit is set, crst pin is controlle d and follows the ?automatic reset transition? ( page 15 ). dck[2:0] cks[2:0] clk a2/ck cclk dc/dc dcclk 0 1 ckstop bit cardck bit dck[2:0] cks[2:0] clk a2/ck cclk dc/dc dcclk 0 1 ckstop bit cardck bit cmdvcc a1/rst crst_sel bit hardware activation
13 4234f?scr?10/05 at83c24 figure 8. crst block diagram with soft activation figure 9. crst block diagram with hardware activation ( cmdvcc pin used) crst 0 1 crst_sel bit = 0 0 1 art bit cardrst bit tb delay see fig 12 a1/rst crst 0 1 0 1 art bit cardrst bit crst_sel bit = 1 hardware activation cmdvcc activation cmdvcc deactivation
14 4234f?scr?10/05 at83c24 activation sequence hardware activation (dc/dc started with cmdvcc ) initial conditions: carddet bit must be configured in accord ance to the smart card connector polarity. it_sel bit, crst_sel bit (see config4 regist er) must be set and cardrst bit (see inter - face register) must be cleared. a smart card must be detected to enable to start the dc/dc (cvcc= 3v or 5v). the hardware activation sequence is started by hardware with cmdvcc pin going high to low. it follows this automatic sequence: ? cio / cc4 / cc8 and io / c4 / c8 are respective ly linked together (iodis bit is cleared). ? the dc/dc is started and cvcc is set according to the a0/3v pin: 5v (class a) if a0/3v is high and 3v (class b) is a0/3v is low. ? cclk signal is enabled (ckstop bit cleared) when cvcc has settled to the programmed voltage (see electrical characte ristics) and the level on a1/rst is 0. the cclk source can be dcclk signal, clk signal , a2/ck si gnals or cardck bit (see figures 5). ? crst signal is linked with a1/rst pin as soon as a1/rst pin level is 0. a rising edge on a1/rst pin set the crst pin. note: 1. the card must be deactivated to change the voltage. figure 10. activation sequence with cmdvcc note: for nds applications, the host usually starts activation with a1/rst = 0. cmdvcc a1/rst cclk cvcc crst cio
15 4234f?scr?10/05 at83c24 software activation (dc/dc st arted with writing in vcard[1:0] bits) and art bit = 1 initial conditions: cardrst bit = 0, ckstop bit =1, iodis bit = 1. the following sequence can be applied: 1. card voltage is set by so ftware to the required value (vcard[1:0] bits in config0 register). this writing starts the dc/dc. 2. wait the end of the dc/dc init with a polling on vcardok bit (status register) or wait for pres/ int to go low if enabled (if it_sel bit = 0 in conf ig4 register). when vcardok bit is set (by hardware), cardio bit should be set by software. 3. ckstop, iodis are programmed by software. ckstop bit is reset to have the clock running. iodis is reset to drive the i/o, c4, c8 pins and the cio,cc4, cc8 pins according to each other. 4. cardrst bit (see interface register) is set by software. automatic reset tran sition description: a 16-bit counter starts when cardrst bit is set. it counts card clock cycles. the crst signal is set when the counter reaches the timer[1-0] value which corresponds to the ?tb? time ( figure 11 ).the counter is reseted when the crst pin is released and it is stopped at the first start bit of the answer to reques t (atr) on cio pin. the cio pin is not checked during the first 200 clock cycles (ta on figure 11 ). if the atr arrives before the counter reaches timer[ 1-0] value, the activation se quence fails, the crst signal is not set and the capture[1-0] register contains th e value of the counter at the arrival of the atr. if the atr arrives after the rising edge on crst pin and before the card clock counter overflows (65535 clock cycles), the activation sequence co mpletes. the capture[1-0] register contains the value of the counter at the arrival of the atr (tc time on figure 11 ). figure 11. software activation with art bit = 1 cvcc crst cclk tc tb ta cio cardrst bit set 1 2 3 4
16 4234f?scr?10/05 at83c24 iso 7816 constraints: ta = 200 card clock cycles 400 card clock cycles< = tb 400 card clock cycles< = tc < = 40000 card clock cycles note: timer[1-0] reset value is 400. software activation (dc/dc started by writing in vcard[1:0] bits) and art bit = 0 the activation sequence is controlled by so ftware using twi commands, depending on the cards to support. for iso 7816 cards, the following sequence can be applied: 1. card voltage is set by so ftware to the required value (vcard[1:0] bits in config0 register). this writing starts the dc/dc. 2. wait of the end of the dc/dc init with a polling on vcardok bit (status register) or wait for pres/ int to go low if enabled (if it_sel bit = 0 in config4 register). when vcardok bit is set (by hardware), cardio bit should be set by software. 3. ckstop, iodis are programmed by software. ckstop bit is reset to have the clock running. iodis is reset to drive the i/o, c4, c8 pins and the cio,cc4, cc8 pins according to each other. 4. crst pin is controlled by software using cardrst bit (see interface register). figure 12. software activation without automatic control (art bit = 0) note: it is assumed that initially vcard[1:0] , cardck, cardio and cardrst bits are cleared, ckstop and iodis are set (those bits are fu rther explained in the registers description) note: the user should check the at83c24 status an d possibly resume the activation sequence if one twi transfer is not acknowledged during the activation sequence. deactivation sequence the card automatic deactivation is triggered when one the following condition occurs: ? icarderr bit is set by hardware cvcc crst cclk cio 2 4 3 1 atr
17 4234f?scr?10/05 at83c24 ? vcarderr bit is set by ha rdware (or by software) ? insert is set and cardin is cleared (card extraction) ? shutdown is set by software ? cmdvcc goes from low to high ? power fail on vcc (see powe rmon bit in config4 register) ? reset pin going low it is a self-timed sequence which can not be interrupted when started (see figure 13 ). each step is separated by a delay based on td equal to 8 periods of the dc/dc clock, typically 2 s: 1. t0: cardrst is cleared, shutdown bit set. 2. t0 + 5 x td:cardck is cleared, ckstop, cardio and iodis are set. 3. t0 + 6 x td: cardio is cleared. 4. t0 + 7 x td: vcard[1-0] = 00. figure 13. deactivation sequence notes: 1. setting icarderr by software does not trigger a deactivation. vcarderr can be used to deactivate the card by software. 2. t1=5 to 5.5*td, and t2=0.5*td to td. transparent mode if the microcontroller outputs iso 7816 signals, a transparent mode allows to connect rst/clk and i/o/c4/c8 signals after an electrical level co ntrol. the at83c24 level shifters adapt the card signals to the smart ca rd voltage selection. the crst and cclk microcontroller signals can be respectively connect ed to the a1/rst and a2/ck pins. the crst_sel bit (in config4 register) select s standard or transparent configuration for the crst pin. cks in config2 allows to select st andard or transparent configuration for the cclk pin. so cclk and crst are independent. a2/ck to a0/3v inputs always give the twi address at reset. the a0/3v pin can be used for twi addressing and easily connect two at83c24 devices on the same twi bus. cvcc crst cclk cio, td cc4, cc8 t1 t2
18 4234f?scr?10/05 at83c24 figure 14. transparent mode description power modes two power-down modes are available to r educe the at83c24 power consumption (see stut - down bit in config1 register and lp bits in config3 register). to enter in the mode number 4 (see table 5 ), the sequence is the following: ? first select the low-power mode by setting the lp bit ? the activation of the shutdown bit can then be done. the at83c24 exits power-down if a software/hardware reset is done or if shutdown bit is cleared. the at83c24 is then active immediately. either a hardware reset or a twi command cleari ng the shutdown bit can cause an exit from power-down. the internal registers retain their value during the shutdown mode. in power-down mo de, the device is sleeping and waiting for a wake up condition. to reduce power consumption, the user should st op the clock on the clk input after setting the shutdown bit. the clock can be enabled again just before exiting shutdown (at least 10 s before a start bit on sda). cclk crst cio i/o a2/ck a1/rst at83c24 smart card crst cclk cc4 microcontroller cc8 cio c4 c8 cc4 cc8 table 5. power modes description mode number shutdown bit lp bit stepreg vcard[1:0] typical supply current description 1 0 x 0 11 160 ma 30 ma step up mode: vcc = 3v, cvcc = 5v, icard = 65ma icard = 0 2 0 x 1 11 70 ma regulator mode: vcc = 5.25v, cvcc = 5v, icvcc = 65ma 3 0 x x 00 3 ma dc/dc off, clk = 10mhz, vcc=3v to 5v 4 1 0 x 00 90 a the twi interface of the at83c24 is active but its analog blocs are switched off to reduce the consumption 5 1 1 x 00 30 a pulsed mode of the internal 3v logic regulator
19 4234f?scr?10/05 at83c24 power monitoring the at83c24 needs only one power supply to run: vcc. if the microcontroller outputs signal s with a different electrical leve l, the host positive supply is connected to evcc. evcc and vcc pins can be connected together if they have the same voltage. ? if evcc and vcc have different electrical levels: the evcc pin and reset pin shou ld be connected with a resist or bridge. reset pin high level must be higher than vih (see table 19) . when evcc drops, reset pin level drops too. a deactivation sequence starts if a card was active. then the at83c24 resets if reset pin stays low. ? if evcc and vcc have the same value, then they should be connected: the at83c24 integrates an internal 3v regulator to feed its logic from the vcc supply. the bit powermon allows the user to select if the in ternal pfd monitors vcc or the internal regu- lated 3v. if the pfd monitors vcc (powermon bi t=0), a deactivation is performed if vcc falls below vpfdp (see vpfdp value in the dat asheet). same deactivation is performed if the internal 3v falls below vpfdp and powermon bit = 1.
20 4234f?scr?10/05 at83c24 registers table 6. config0 (config byte 0) 7 6 5 4 3 2 1 0 1 0 atrerr insert icarderr vcarderr vcard1 vcard0 bit number bit mnemonic description 7-6 1-0 these bits cannot be programmed and are read as 1-0. 5 atrerr answer to reset interrupt this bit is set when the card clock counter overflows (no falling edge on cio is received before the overflow of the card clock counter). this bit is cleared by hardware when th is register is read. it can be set by software for test purpose. the reset value is 0. 4 insert card insertion interrupt this bit is set when a card is inserted or extracted: a change in cardin value filtered according to cds[2-0]. after power up, if the level on cpres pin is 0, then insert bit is set. it can be set by software for test purpose. this bit is cleared by hardware when this register is read. it cannot be cleared by software. the reset value is 0. 3 icarderr card over current interrupt this bit is set when an over current is detected on cvcc. it can be set by software for test purpose (no card deactivation is performed, no it is performed). this bit is cleared by hardware when this register is read. it cannot be cleared by software. the reset value is 0. 2 vcarderr card out of range voltage interrupt this bit is set when the output voltage goes out of the voltage range specified by vcard field. it can be set by software for test purpose and deactivate the card. this bit is cleared by hardware when this register is read. it cannot be cleared by software. the reset value is 0. 1-0 vcard[1:0] card voltage selection vcard[1:0] = 00: 0v vcard[1:0] = 01: 1.8v (see stepreg bit) vcard[1:0] = 10: 3v vcard[1:0] = 11: 5v vcard[1:0] writing to 1.8v, 3v, 5v starts the dc/dc if a card is detected. vcard[1:0] writing to 0 stops the dc/dc. no card deactivation is performed when the voltage is changed between 1.8v, 3v or 5v. the microcontroller should deactivate the card before changing the voltage. the reset value is 00.
21 4234f?scr?10/05 at83c24 table 7. config 1 (config byte 1) 7 6 5 4 3 2 1 0 x art shutdown carddet pullup cds2 cds1 cds0 bit number bit mnemonic description 7 x this bit should not be set. 6 art automatic reset transition set this bit to have the crst pin changed according to activation sequence. clear this bit to have the crst pin i mmediately following the value programmed in cardrst. the reset value is 0. 5 shutdown shutdown set this bit to reduce the power cons umption. an automatic de-activation sequence will be done. clear this bit to enable vcard[1:0] selection. the reset value is 0. 4 carddet card presence detection polarity set this bit to indicate the card pres ence detector is closed when no card is inserted (cpres is low). clear this bit to indicate the card presence detector is open when no card is inserted (cpres is high).changing carddet will set insert bit (see config0) even if no card is inserted or extracted. the reset value is 0. 3 pullup pull-up enable set this bit to enable the internal pull- up on the cpres pin. this allows to minimize the number of external components. clear this bit to disable the internal pull-up and minimize the power consumption when the card detection contact is on. then an external pull-up must be connected to v cc (typically a 1 m resistor). the reset value is 1. 2-0 cds[2:0] card detection filtering cpres is sampled by the master clock provided on clk input. a change on cpres is detected after: cds[2-0] = 0: 0 sample (1) cds[2-0] = 1: 4 identical samples cds [2-0] = 2: 8 identical samples (reset value) cds[2-0] = 3: 16 identical samples cds[2-0] = 4: 32 identical samples cds[2-0] = 5: 64 identical samples cds[2-0] = 6: 128 identical samples cds[2-0] = 7: 256 identical samples the reset value is 2. note: when cds[2-0] = 0 and it_sel = 0, pres/ int = 1 when no card is present and pres/ int = 0 when a card is inserted even if clk is stopped. this can be used to wake up the external microcontroller and restart clk when a card is inserted in the at83c24. if cds[2-0] = 0, it_sel = 1 and clk is stopped, a card insertion or extraction has no effect on pres/ int pin.
22 4234f?scr?10/05 at83c24 notes: 1. when this register is changed, a special logic insures no glitch occurs on the cclk pin and actual configuration changes can be delayed by half a period to two periods of cclk. 2. cclk must be stopped with ckstop bit before s witching from cks = (0, 1, 2, 3, 6, 7) to cks = (4, 5) or vice versa. 3. when dck = 0, only cks=4 and cks=5 are allowed. 4. the user can?t directly select a2 or a2/2 after a reset or when switching from cks = (0, 1, 2, 3, 6, 7) to cks = (4, 5). to select a2, the user sh ould select a2/2 first and after a2. to select a2/2, the user should select a2 first and after a2/2. table 8. config2 (config byte 2) 7 6 5 4 3 2 1 0 x dck2 dck1 dck0 x cks2 cks1 cks0 bit number bit mnemonic description 7 x this bit should not be set. 6-4 dck[2:0] dc/dc clock prescaler factor dcclk is the dc/dc clock. it is the di vision of clk input by dck prescaler. dck = 0: prescaler factor equals 1 (clk = 4 to 4.61mhz) dck [2:0] = 1: prescaler factor equals 2 (clk = 7 to 9.25mhz) dck [2:0] = 2: prescaler factor equals 4 (clk = 14 to 18.5 mhz) dck [2:0] = 3: prescaler factor equals 6 (clk = 21 to 27.6 mhz) dck [2:0] = 4: prescaler factor equals 8 (clk = 28 to 34.8 mhz) dck [2:0] = 5: prescaler factor equals 10 (clk = 35 to 43 mhz) dck [2:0] = 6: prescaler factor equals 12 (clk = 43.1 to 48 mhz) dck [2:0] = 7: reserved the reset value is 1. dcclk must be as close as possible to 4 mhz with a duty cycle of 50%. dck must be programmed before starting the dc/dc. the other values of clk are not allowed. dck has to be properly configured before resetting the stepreg bit. 3 x this bit should not be set. 2-0 cks[2:0] card clock prescaler factor cks [2:0] = 0: cclk = clk (then the maximum frequency on clk is 24 mhz) cks [2:0] = 1: cclk = dcclk (dc/dc clock) cks [2:0] = 2: cclk = dcclk / 2 cks [2:0] = 3: cclk = dcclk / 4 cks [2:0] = 4: cclk = a2 cks [2:0] = 5: cclk = a2 / 2 cks [2:0] = 6: cclk = clk / 2 cks [2:0] = 7: cclk = clk / 4 the reset value is 0.
23 4234f?scr?10/05 at83c24 table 9. config3 (config byte 3) 7 6 5 4 3 2 1 0 eauto vext1 vext0 iccadj lp x x x bit number bit mnemonic description 7-5 eauto vext1 vext0 evcc voltage configuration: eauto vext1 vext0 0 0 0 evcc = 0 the regulator is switched off. 0 0 1evcc = 2.3v 0 1 0 evcc = 1.8v 0 1 1 evcc = 2.7v 1 x x evcc voltage is the level detected on i/o input pin. if evcc is supplied from the external ev cc pin, the user can switch off the internal evcc regulator to decrease the consumption. if evcc is switched off, and no external evcc is supplied, the at83c24 is inactive until a hardware reset is done. the reset value is 100. 4 iccadj ci cc overflow adjust this bit controls the dc/dc sensitivity to any overflow current . set this bit to decrease the dc/dc sensitivity (ci cc_ovf is increased by about 20%, see electrical characteristics). the start of the dc/dc with a high current load is easier. clear this bit to have a normal configuration. the reset value is 0. 3 lp low-power mode set this bit to enable low-power mo de during shutdown mode (pulsed mode activated). clear this bit to disable low-power mode during shutdown mode. the activation reference is the following: ? first select the low-power mode by setting lp bit. ? the activation of shutdown bit can then be done. this bit as no effect when shutdown bit is cleared. the reset value is 0. 2 x this bit should not be set. 1 x this bit should not be set. 0 x this bit should not be set.
24 4234f?scr?10/05 at83c24 table 10. config4 (config byte 4) 7 6 5 4 3 2 1 0 x x x stepreg int_pullup powermon it_sel crst_sel bit number bit mnemonic description 7-5 x-x-x these bits should not be set. 4 stepreg step regulator mode clear this bit to enable the automatic step-up converter (cvcc is stable even if vcc is not higher than cvcc). set this bit to permanently disable the step-up converter (c vcc is stable only if vcc is sufficiently higher than cvcc). this bit must be set before activating the dc/ dc converter if no external coil is present. the reset value is 0. this bit must always be set if no external coil is used 3 int_pullup internal pull-up set this bit to activate the internal pul l-up (connected internally to evcc) on pres/ int pin. clear this bit to deactivate the internal pull-up. pres/ int is an open drain output with a programmable internal pull up. the reset value is 0. 2 powermon power monitor set this bit to monitor any glitch on the digital supply voltage (dvcc) of the at83c24. clear this bit to monitor any glitch on vcc. the reset value is 0. 1 it_sel interrupt select set this bit to disable insert and vcard_int interrupts. then pres/ int is pulled up when a card is present and no error is detected. clear this bit to have all the in terrupt sources enabled and active low. it_sel must be set to enable a hardware activation with cmdvcc . the reset value is 0. 0 crst_sel card reset selection set this bit to have the crst pin driven by hardware through the a1 pin (only with hardware activation). clear this bit to have the crst pin driven by software through the cardrst bit. crst_sel must be set when cmdvcc is used (hardware activation). the reset value is 0.
25 4234f?scr?10/05 at83c24 table 11. interface (interface byte) 7 6 5 4 3 2 1 0 0 iodis ckstop cardrst cardc8 cardc4 cardck cardio bit number bit mnemonic description 7 0 this bit should not be set. 6 iodis card i/o isolation set this bit to drive the cio, cc4, cc8 pins accordi ng to cardio, cardc4, cardc8 respectively and to put i/o, c4, c8 in hi-z. this can be used to have the i/o , and c4 and c8 pins of the host communicating with another at83c24 interface, while cio, cc4 and cc8 are driven by software (or if the card is in standby or power-down modes). clear this bit to drive the i/o/cio, c4/cc4 and c8/cc8 pi ns according to each other. this can be used to activate asynchronous cards. the reset value is 1. 5 ckstop card clock stop set this bit to stop cclk according to cardck. this can be used to set asynchronous cards in power-down mode (gsm) or to drive cclk by software. clear this bit to have cclk running according to cks. this can be used to activate asynchronous cards. note: 1. when this bit is changed a special logic ensures that no glitch occurs on the cclk pin and actual configuration changes can be del ayed by half a period to two periods of cclk. 2. ckstop must be set before swit ching on the dc/dc with vcard[1:0]. the reset value is 1. 4 cardrst card reset set this bit to enter a reset sequence according to art bit value. clear this bit to drive a low level on the crst pin. the reset value is 0. 3 cardc8 card c8 set this bit to drive the cc8 pin high with the on-chip pu ll-up (according to iodis bit value). the pin can then be an input (read in status register). clear this bit to drive a low level on t he cc8 pin (according to iodis bit value). the reset value is 0. 2 cardc4 card c4 set this bit to drive the cc4 pin high with the on-chip pu ll-up (according to iodis bit value). the pin can then be an input (read in status register). clear this bit to drive a low level on t he cc4 pin (according to iodis bit value). the reset value is 0. 1 cardck card clock set this bit to set a high level on the cclk pin (according to ckstop bit value). clear this bit to drive a low level on the cclk pin. the reset value is 0. 0 cardio card i/o set this bit to drive the cio pin high with the on-chip pull-up (according to iodis bit value). the pin can then be an input (read in status register). clear this bit to drive a low level on t he cio pin (according to iodis bit value). the reset value is 0.
26 4234f?scr?10/05 at83c24 reset value = 0x00000001 table 12. status (status byte) 7 6 5 4 3 2 1 0 cc8 cc4 cardin vcardok x vcard_int crst cio bit number bit mnemonic description 7 cc8 card cc8 this bit provides the actual level on the cc8 pin when read. the reset value is 0. 6 cc4 card cc4 this bit provides the actual level on the cc4 pin when read. the reset value is 0. 5 cardin card presence status this bit is set when a card is detected. it is cleared otherwise. 4 vcard_ok card voltage status this bit is set by the dcdc when the output voltage remains within the voltage range specified by vcard[1:0] bits. it is cleared otherwise. the reset value is 0. 3 x this bit should not be set. 2 vcard_int card voltage interrupt this bit is set when vcard_ok bit is set. this bit is cleared when r ead by the microcontroller. the reset value is 0. 1 crst card rst this bit provides the actual level on the crst pin when read. the reset value is 0. 0 cio card i/o this bit provides the actual level on the cio pin when read. the reset value is 0. table 13. timer 1 (timer msb) 7 6 5 4 3 2 1 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit number bit mnemonic description 7 - 0 bits 15 - 8 timer msb (bits 15 to 8)
27 4234f?scr?10/05 at83c24 reset value = 0x10010000 reset value = 0x00000000 reset value = 0x00000000 table 14. timer 0 (timer lsb) 7 6 5 4 3 2 1 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit number bit mnemonic description 7 - 0 bits 7 - 0 timer lsb (bits 7to 0) table 15. capture 1 (capture msb) 7 6 5 4 3 2 1 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit number bit mnemonic description 7 - 0 bits 15 - 8 see ?software activation with art = 1?, page 15 . table 16. capture 0 (capture lsb) 7 6 5 4 3 2 1 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit number bit mnemonic description 7 - 0 bits 7 - 0 see ?software activation with art = 1?, page 15 .
28 4234f?scr?10/05 at83c24 electrical characteristics absolute maximum ratings * (**) exposed die attached pad must be soldered to ground thermal resistor are measured on multilayer pcb with 0 m/s air flow. (***) including sh ortages between an y groups of sm art card pins. ac/dc parameters evcc connected to host power supply: from 1.6v to 5.5v. t a = -40 c to +85 c; v ss = 0v; v cc = 3v to 5.5v. class a card supplied with cvcc = 4.75 to 5.25v for at83c24nds class a card supplied with cvcc = 4.6 to 5.25v for at83c24 class b card supplied with cvcc = 2.8v to 3.2v class c card supplied with cvcc = 1.68v to 1.92v ambient temperature under bias: ........... ..........-40 c to 85 c storage temperature: ................................... -65 c to +150 c voltage on vcc: ........................................ v ss -0.5v to +6.0v voltage on scib pins (***): ......... cvss -0.5v to cvcc + 0.5v voltage on host interface pins: ....... vss -0.5v to evcc + 0.5v voltage on other pins: ...................... vss -0.5v to vcc + 0.5v power dissipation: .......................................................... 1.5w thermal resistor of qfn pack - age..(**)............................35c/w thermal resistor of so package.................................48c/w *notice: stresses at or above those listed under ?absolute maximum ratings? may cause permanent dam - age to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. power dissipation value is based on the maxi - mum allowable die temperature and the thermal resistance of the package. table 17. core (vcc) symbol parameter min typ max unit test conditions v pfdp power fail high level threshold 2.4 2.5 2.6 v v pfdm power fail low level threshold 2.25 2.35 2.45 v t rise, t fall v dd rise and fall time 1 s 600s not tested. table 18. host interface (i/o, c4, c8, clk, a2, a1, a0, cmdvcc , pres/ int ) symbol parameter min typ max unit test conditions v il input low-voltage -0.5 0.3 x evcc 0.25 x evcc v evcc from 2.7v to vcc evcc from 1.6 to 2.7v v ih input high voltage 0.7 x evcc evcc + 0.5 v eauto=0 eauto=1 evcc from 1.6v to vcc
29 4234f?scr?10/05 at83c24 v ol output low-voltage (i/o, c4, c8, pres/ int ) 0.05 0.4 v v i ol = -100 a i ol = -1.2 ma v oh output high voltage (c4, c8, pres/ int ) v oh on i/o depends on external pull up value 0.8 x evcc evcc v evcc from 1.6v to vcc i oh = 100 a ei cc extra supply current +3 ma c l = 100 nf r pres/int pres/ int weak pull-up output current 300 330 360 ? short to vss int_pullup = 0: internal pull-up active. evcc evcc pin not connected to a power supply vpeak - 10 mv vpeak vpeak + 25 mv v c l = 100 nf, eicc = +3 ma vpeak on i/o from 1.6v to vcc eauto = 1: min duration 1s, min frequency 0.1hz, spikes <50ns are filtered. evcc evcc pin connected to a power supply vpeak - 200mv eauto = 1 clk clock signal for at83c24 4 48 mhz if dck[2:0] =0 (clk=4mhz to 4.61mhz), a duty cycle of 50% is needed. clk clock signal for at83c24nds 18 48 mhz no constrainst on duty cycle table 18. host interface (i/o, c4, c8 , clk, a2, a1, a0, cmdvcc , pres/int ) (continued) symbol parameter min typ max unit test conditions table 19. host interfac e (scl, sda, reset) symbol parameter min typ max unit test conditions v il input low-voltage -0.5 1.9 0.3 x vcc v vcc > 4.5v vcc <= 4.5v v ih input high voltage 3 0.7 x vcc vcc + 0.5 v vcc > 4.5v vcc <= 4.5v v ol output low-voltage 0.4 v i ol = -3 ma v hist input trigger hysteresis 0.1 x vcc table 20. smart card class a symbol parameter min typ max unit test conditions ci cc card supply current capability 65 65 ma vcc=3v to 5.5v, stepreg=0 vcc > 5.35v, stepreg = 1 ci cc _ovf card supply current overflow: iccadj = 0 (reset value) iccadj = 1 66 66 120 130 130 150 ma vcc from 3 to 5.5v
30 4234f?scr?10/05 at83c24 notes: 1. capacitor: x7r type or x5r type, max esr value is 30m (100khz-100mhz), replacing 3.3f by 2.2f in parrallel with 1f is better for esr and noise reduction. ripple on cvcc 60 150 200 350 mv 0 < icard < 60ma c l =10f for at83c24 0 < icard < 65ma c l = 3.3f for at83c24nds spikes on cvcc 4.6 5.3 v max. charge 40 na.s max. duration 400 ns max. icard variation 200 ma vcardok up vcardok high level threshold 4.8 4.9 v vcardok down vcardok low level threshold 4.6 4.75 4.8 4.8 v at83c24 at83c24nds t vhl cvcc valid to 0 180 500 250 750 s icard = 0, vcc > v pfdp c l = 3.3 f icard = 0 c l = 10 f icard = 0 (see note 1) t vlh cvcc 0 to valid 180 110 240 170 250 250 300 250 s vcc = 3v, c l = 3.3f icard = 65 ma icard = 0 ma vcc = 3v, c l = 10f icard = 65 ma icard = 0 ma table 20. smart card class a symbol parameter min typ max unit test conditions table 21. smart card class b symbol parameter min typ max unit test conditions ci cc card supply current capability 65 65 ma vcc=3v to 5.5v, stepreg=0 vcc > 5.35v, stepreg = 1 ci cc _ovf card supply current overflow: iccadj = 0 (reset value) iccadj = 1 66 66 130 140 140 150 ma vcc from 3.0 to 5.5v ripple on cvcc 60 200 350 mv 0 < icard < 65ma c l =10f 0 < icard < 65ma c l = 3.3f spikes on cvcc 2.76 3.24 v maxi. charge 40 na.s max. duration 400 ns max. variation icard 200ma vcardok up vcardok high level threshold 2.8 3 v vcardok down vcardok low level threshold 2.76 2.9 v t vhl cvcc valid to 0 130 400 250 500 s icard = 0, vcc > v pfdp c l = 3.3 f icard = 0 (see note 1) c l = 10 f icard = 0
31 4234f?scr?10/05 at83c24 notes: 1. capacitor: x7r type or x5r type, max esr value is 30m (100khz-100mhz), replacing 3.3f by 2.2f in parrallel with 1f is better for esr and noise reduction. notes: 1. capacitor: x7r type or x5r type, max esr value is 30m (100khz-100mhz), replacing 3.3f by 2.2f in parrallel with 1f is better for esr and noise reduction. t vlh cvcc 0 to valid 140 110 130 100 250 250 250 250 s vcc = 3v, c l = 3.3f icard = 65 ma icard = 0 ma vcc = 3v, c l = 10f icard = 60 ma icard = 0 ma table 22. smart card class c symbol parameter min typ max unit test conditions ci cc card supply current capability 40 ma vcc = 3v ci cc _ovf card supply current overflow: iccadj = 0 (reset value) iccadj = 1 45 ma spikes on cvcc 1.68 1.92 v vcardok up vcardok high level threshold 1.75 1.8 v vcardok down vcardok low level threshold 1.7 1.75 v t vhl cvcc valid to 0 180 300 s icard = 0, c l = 10 f (1) cvcc = 1.8v to 0.4v t vlh cvcc 0 to valid 200 100 50 60 300 150 80 100 s icard = 40ma, c l = 10 f (1) icard = 0, c l = 10 f (1) icard = 40ma, c l = 3.3 f (1) icard = 0, c l = 3.3 f (1) cvcc = 0.4 to vcardok table 21. smart card class b symbol parameter min typ max unit test conditions table 23. smart card clock (cclk pin) symbol parameter min typ max unit test conditions v ol output low-voltage 0 0.4 v i ol = -200 a class a&b&c v oh output high voltage cvcc - 0.45 0.7cvcc cvcc cvcc v i oh = +200 a class a&b class c i os short circuit current -30 30 ma short to gnd or cvcc t r t f rise and fall time 16 22.5 50 ns c l = 30 pf class a c l = 30 pf class b c l = 30 pf class c measurement between 10% and 90% of cvcc
32 4234f?scr?10/05 at83c24 rise and fall slew rate 0.2 0.12 v/ns class a cclk from 0.5 to 4.2v class b cclk from 0.5 to 0.85 x cvcc low level voltage stability (taking into account pcb design) -0.25 0.5 v class a&b&c high level voltage stability (taking into account pcb design) 4.2 2.35 cvcc-0.4 cvcc+0.25 cvcc+0.25 cvcc+0.25 v cvcc = class a cvcc = class b class c cclk smart card clock frequency 24 mhz c l = 30pf, clk=48mhz table 23. smart card clock (cclk pin) (continued) symbol parameter min typ max unit test conditions table 24. smart card i/o (cio, cc4, cc8 pins) symbol parameter min typ max unit test conditions v il input low-voltage -0.3v 0.8 v i il = 500 a i il input low current 700 a cvcc = class a&b&c v ih input high voltage 0.6 x cvcc 0.7 x cvcc cvcc cvcc v cvcc = class a cvcc = class b & c i ih input high current -20 +20 a v ol output low-voltage 0 0.45 0.3 0.3 v i ol = -1 ma class a i ol = -1 ma class b i ol = -1 ma class c v oh output high voltage 0.75 x cvcc 0.9 x cvcc cvcc cvcc v i oh = 40 a class a&b&c i oh = 0 a, class a&b i os output short circuit current -15 +15 ma short to gnd or cvcc low level voltage stability (taking into account pcb design) -0.25 -0.25 -0.25 0.6 0.4 0.4 v class a class b class c high level voltage stability (taking into account pcb design) cvcc-0.5 cvcc+0.25 v cvcc = class a&b&c t r t f output rise and fall time 0.1 s c l = 65 pf class a: measurement between 0.6v and 70% of cvcc class b & c: measurement between 0.4v and 70% of cvcc t r t f input rise and fall time 1 s c l = 65 pf
33 4234f?scr?10/05 at83c24 table 25. smart card rst (crst pin) symbol parameter min typ max unit test conditions v ol output low-voltage 0 0 0.12 x cvcc 0.4 0.2 v i ol = -20 a class a&b&c i ol = -200 a class a i ol = -200 a class b&c v oh output high voltage 0.9*cvcc cvcc v i oh = 200 a class a&b&c i os output high current -15 +15 ma short to gnd or cvcc t r t f rise and fall time 0.1 s c l = 30pf measurement between 10% and 90% of cvcc low level voltage stability (taking into account pcb design) -0.25 0.50v 0.30v 0.30v v class a class b class c high level voltage stability (taking into account pcb design) 4.2 2.35 cvcc-0.4 cvcc+0.25 v class a class b class c table 26. card presence symbol parameter min typ max unit test conditions r cpres cpres weak pull-up output current 300 330 360 ? short to vss pullup = 1: internal pull-up active table 27. twi (sda, scl pins) symbol parameter min typ max unit test conditions t su;dat data set-up time 20 10 ns not tested t hd;dat data hold time 10 0 ns not tested t fda fall time on sda signal 50 ns not tested
34 4234f?scr?10/05 at83c24 typical application figure 1. typical standard mode application diagram for 3 at83c24 (up to 8 at83c24 if needed) note: 1. the external resistor on i/o can be removed if the host pin has an internal resistor. 100nf xtal1 xtal2 1uf host cvss cvss 2.2f c1 c2 c10 4.7h vss vss pres/int clk crst cpres cio, cc4, cc8 cclk cvcc, at83c24 scl sda i/o, c4, c8 pres/int clk cvcc, scl sda i/o, c4, c8 pres/int clk vss vcc cvcc, li cvss scl sda i/o, c4, c8 card 3 v cc microcontroller twi int0 px.y l1 reset rst v cc 4 to 48 mhz reset reset v cc vss v cc vss v cc a2/ck a1/rst a0/3v a2/ck a1/rst a0/3v a2/ck a1/rst a0/3v evcc evcc evcc evcc evcc evcc vss dvcc vss dvcc vss dvcc 100nf 100nf 100nf vcc 2.2uf cvss c3 100nf 1uf cvss cvss c5 c11 2.2uf cvss c6 100nf 1uf cvss cvss c8 c12 2.2uf cvss c9 vss reset pullup sda, scl pullups see note for i/o pull up crst cpres cio, cc4, cc8 cclk card 2 crst cpres cio, cc4, cc8 cclk card 1 at83c24 at83c24 100nf c13 vss 2.2f c4 4.7h vss vcc li cvss l2 vss 100nf c14 vss v cc 2.2f c5 4.7h vss li cvss l3 vss 100nf c15 vss v cc vcc cvccin cvccin cvccin

36 4234f?scr?10/05 at83c24 typical nds application figure 2. typical nds standard mode application diagram for 1 at83c24nds. note: 1. the external resistor on i/o can be remo ved if the host pin has an internal resistor. 2. the internal pull up on pres/int is disabled during reset (recommended external 20kohms pull up). 3. refer to application note for at83c24nds software configuration. 100nf xtal1 xtal2 1uf host cvss cvss 2.2f c1 c2 c10 4.7h vss vss pres/int clk vss v cc cvcc li cvss scl sda i/o, c4, c8 v cc microcontroller twi int0 px.y l1 reset rst v cc 18.432 or 27mhz a2/clk a1/rst a0/3v evcc evcc vss dvcc 100nf vcc 2.2uf cvss c3 vss reset pullup sda, scl pullups see note1 for i/o pull up crst cpres cio, cc4, cc8 cclk at83c24nds 100nf c13 vss px.y px.y px.y vss card smart card 1 cvccin present see note 2
37 4234f?scr?10/05 at83c24 ordering information part number supply voltage temperature range package packing at83c24b-prtil (2) 3v to 5.5v industrial qfn28 tray at83c24b-prril (2) 3v to 5.5v industrial qfn28 tape&reel at83c24b-prtim (2) 4.00v to 5.5v industrial qfn28 tray at83c24b-prrim (2) 4.00v to 5.5v industrial qfn28 tape&reel at83c24b-tisil 3v to 5.5v industrial so28 stick at83c24b-tiril 3v to 5.5v industrial so28 tape&reel at83c24b-tisim 4.00v to 5.5v industrial so28 stick at83c24b-tirim 4.00v to 5.5v industrial so28 tape&reel at83c24nds-prtil (1)(2) 3v to 5.5v industrial qfn28 tray at83c24nds-prril (1)(2) 3v to 5.5v industrial qfn28 tape&reel at83c24nds-prtim (1)(2) 4.00v to 5.5v industrial qfn28 tray at83c24nds-prrim (1)(2) 4.00v to 5.5v industrial qfn28 tape&reel AT83C24NDS-TISIL (1) 3v to 5.5v industrial so28 stick at83c24nds-tiril (1) 3v to 5.5v industrial so28 tape&reel at83c24nds-tisim (1) 4.00v to 5.5v industrial so28 stick at83c24nds-tirim (1) 4.00v to 5.5v industrial so28 tape&reel at83c24b-prtul (2) 3v to 5.5v industrial & green qfn28 tray at83c24b-prrul (2) 3v to 5.5v industrial & green qfn28 tape&reel at83c24b-prtum (2) 4.00v to 5.5v industrial & green qfn28 tray at83c24b-prrum (2) 4.00v to 5.5v industrial & green qfn28 tape&reel at83c24b-tisul 3v to 5.5v industrial & green so28 stick at83c24b-tirul 3v to 5.5v industrial & green so28 tape&reel at83c24b-tisum 4.00v to 5.5v industrial & green so28 stick at83c24b-tirum 4.00v to 5.5v industrial & green so28 tape&reel at83c24nds-prtul (1)(2) 3v to 5.5v industrial & green qfn28 tray at83c24nds-prrul (1)(2) 3v to 5.5v industrial & green qfn28 tape&reel at83c24nds-prtum (1)(2) 4.00v to 5.5v industrial & green qfn28 tray at83c24nds-prrum (1)(2) 4.00v to 5.5v industrial & green qfn28 tape&reel
38 4234f?scr?10/05 at83c24 note: 1. enhanced ac/dc parameters, see first page for differences between at83c24 and at83c24nds. 2. refer to index mark for proper placement. at83c24nds-tisul (1) 3v to 5.5v industrial & green so28 stick at83c24nds-tirul (1) 3v to 5.5v industrial & green so28 tape&reel at83c24nds-tisum (1) 4.00v to 5.5v industrial & green so28 stick at83c24nds-tirum (1) 4.00v to 5.5v industrial & green so28 tape&reel part number supply voltage temperature range package packing
39 4234f?scr?10/05 at83c24 package drawings qfn28
so28
41 4234f?scr?10/05 at83c24 datasheet change log changes from 4234a-05/03 to 4234b-02/04 1. addition of crst, cio, cclk controllers descriptions, page 10 . 2. update of hardware\software activation description, page 14 . 3. suppression of low voltage regulator mode for power down modes, page 18 . 4. modification of clock values in config2 regsiter, page 22. 5. addition of a point on qfn pinout view, page2. 6. update of electrical characteristics, page 28 . changes from 4234b-02/04 to 4234c - 04/04 1. addition of references in ordering information 2. update of evcc description 3. update of carddet bit and insert bit description changes from 4234c-04/04 to 4234d - 07/04 1. update for rev 4 silicon version (index 4 on component). 2. software workaround for a2 or a2/2 selection in cks register. 3. max speed on io/cio transfer 4. new conditions for hardware activation (see it_sel). 5. so28 drawing package (error with so32). 6. adjusted electrical parameters for nds compliance, pages 28, 29, 30. changes from 4234d-04/04 to 4234e - 09/04 1. qfn28 new package drawing. 2. clock input parameters for at83c24 and at83c24nds. changes from 4234e - 09/04 to 4234f - 10/05 1. updated green product ordering information.
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